Design of Low Power and High Speed CMOS Fingerprint Sensor
نویسنده
چکیده
This paper proposes two topics for a high performance fingerprint sensor. A modified capacitive detection circuit of charge sharing scheme is proposed, which shows 40% reduction of power consumption and 90% improvement of difference between a ridge and valley sensing voltage than typical scheme. This paper also proposes an effective fingerprint identification system with hardware unit (thinning processor) for thinning stage processing of a verification algorithm based on minutiae. Each step of a fingerprint algorithm is analyzed on FPGA and ARMulator. The proposed scheme just needs 56,000 cycles for a thinning processing in 160x192 pixel array and the layout area is 0.541 mm 2 at 0.35μm CMOS process.
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